1. Technical Field
This invention relates to a semiconductor device having a multilayer interconnect structure and a manufacturing process therefor.
2. Related Art
FIG. 21 is a cross-sectional view illustrating the configuration of a conventional semiconductor device. The semiconductor device 200 shown in FIG. 21 will be manufactured in accordance with the following procedure.
First, on a silicon substrate (not shown) are formed an SiO2 film 201 and a SiC barrier dielectric film 203. On the barrier dielectric film 203 is then deposited a porous SiOC film as a first Low-k (low dielectric constant) film 205 to a thickness of about 70 to 200 nm. On the first Low-k film 205 is deposited a hard mask SiO2 film (not shown) to a thickness of about 50 to 150 nm. Then, the hard mask SiO2 film and the porous SiOC film as the first Low-k film 205 are etched with a fluorocarbon based gas and ashed by a photolithography process, to form an interconnect trench. After forming a barrier metal film 211 and a copper interconnect 213 in the interconnect trench, an SiC film is formed as a barrier dielectric film 207. Then, on the film is further formed a porous SiOC film as a second Low-k film 209, which is processed as described above, to form a via hole 215. Thus, there is provided the semiconductor device 200 shown in FIG. 21. Subsequently, a metal film is buried in the via hole 215 to form a via plug (not shown). The process is repeated to form a multilayer interconnect.
However, in the manufacturing process, as a dielectric constant of the insulating interlayer is decreased, film damage due to processing becomes more significant. Specifically, the process of etching and ashing with a fluorocarbon gas leads to formation of a damaged layer 217 in the exposed area in the first Low-k film 205 and the second Low-k film 209. In the area of the damaged layer 217, Si—CH3 bonds in the Low-k film are broken, leading to increase in a dielectric constant of the Low-k film. Furthermore, since a barrier dielectric film 203 with a relatively higher specific dielectric constant exists on the copper interconnect 213, it is difficult to reduce an effective dielectric constant.
In addition, peeling may occur in a stacked portion where on a layer in which the copper interconnect 213 is to be formed, that is, an interconnect layer, a layer with via plug and a smaller metal area than the interconnect layer is formed. Specifically, adhesiveness is poor between the porous SiOC film as the second Low-k film 209 and the SiC film as the barrier dielectric film 207. Therefore, during a T/C (thermal cycle) test after forming a multilayer interconnect and assembling, the films may be peeled due to a difference in a thermal expansion coefficient between the films, leading to a peeled interface 219.
Thus, there has been proposed application of metal cap technique on an interconnect instead of a barrier dielectric film.
FIG. 22 is a cross-sectional view illustrating the configuration of such a semiconductor device. The semiconductor device 210 shown in FIG. 22 does not have a barrier dielectric film 207 in contrast to the semiconductor device 200 shown in FIG. 21, and thus requires an etching stopper during forming a via hole. Therefore, the semiconductor device 210 has a cap metal film 221 over the copper interconnect 213. Over the cap metal film 221 is formed a Cu plug consisting of a barrier metal film 225 and a Cu film 227, on which is formed a cap metal film 229.
The semiconductor device 210 shown in FIG. 22 will be manufactured in accordance with the following process. On an SiO2 film (not shown) is formed an SiC barrier dielectric film 203, on which is then formed a porous SiOC film as a Low-k film. Then, an SiO2 film is formed on the porous SiOC film, to obtain a first stacked film 233. Subsequently, the first stacked film 233 is processed by using photolithography technique, to form an interconnect trench. Then, there are sequentially formed a barrier metal film 211, a Cu seed (not shown) and a Cu plating film to be a copper interconnect 213, and then an interconnect is formed in the trench by CMP. Next, a CoWP layer as a cap metal film 221 is formed on the interconnect by selective growth.
Then, as described above, on the cap metal film 221 is formed a second stacked film 235, in which is then formed a via hole. After forming a plug consisting of a barrier metal film 225 and a Cu film 227 in the via hole, a CoWP layer as a cap metal film 229 is formed on the plug by selective growth.
Japanese patent application NO. 2003-152077 has disclosed that in a multilayer interconnect structure formed by a dual damascene process, a tungsten film is formed as a cap metal film and the tungsten film on the bottom of a contact hole is removed.